Vertical chip stacking could lead to more powerful and energy-efficient phones

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Vertical chip stacking could lead to more powerful and energy-efficient phones

Things looked bad enough for Huawei in May 2019 when the U.S. put it on the entity list as a national security threat. As a result, Huawei could no longer access its U.S. supply chain. But exactly one year later, a change made to U.S. export rules prevented any foundry using U.S. technology to build chips from shipping cutting-edge components to Huawei.

Even the chips that Huawei itself designed through its HiSilicon unit were not allowed to be shipped to the manufacturer which forced Huawei to ration its Kirin 9000 5G chips. And for some models, it has had to turn to Qualcomm’s Snapdragon 888 but without support for 5G. And with the chip industry moving to the 3nm process node next year, how can Huawei’s phones stay competitive if it remains banned from receiving cutting-edge chips?

Huawei plans on looking at chip stacking to stay competitive

According to a Weibo post (via Gizchina), Huawei’s current rotating chairman Guo Ping recently said at the 2021 annual report conference that the company will use chip stacking technologies allowing it to use SoCs built using less-advanced processes and still match the performance of chips made using more advanced process nodes. There are some caveats that Huawei will have to deal with if it follows through on this plan.

Stacking chips will take up more “space” inside a phone and could also generate additional heat. Additionally, this technology could leave less space to squeeze in a large-capacity battery. As you can imagine, chip stacking is the process of mounting chips vertically to increase performance and to better use available space.

While taking questions, the Huawei executive hinted that the company can be self-sustaining when it comes to chips noting that, “In 2019, Huawei’s mobile phone shipments were 120 million units, which means that 120 million mobile phones need chips. In 2019, Huawei’s 5G base station shipments were 1 million units. If each base station needs one chip, it needs 1 million. The two orders of magnitude are completely different. Huawei can be competitive in future products. We will continue to work in this direction.”

Earlier this month, Nikkei Asia reported that three big-name companies that run foundries, TSMC, Samsung, and Intel, announced the creation of a consortium that will focus on advanced chip packaging and chip stacking. Currently, adding more transistors to a chip is the way to produce more powerful components. But eventually, shrinking the size of transistors will reach a point where it can’t be done anymore and that will mean the end of Moore’s Law.

Advances in chip packaging could keep Moore’s Law alive

You might have heard of Moore’s Law. It is an observation made by Intel and Fairchild Semiconductor co-founder Gordon Moore. In 1965, Moore realized that the number of transistors on a dense integrated circuit were doubling every year. By 1975, Moore revised Moore’s Law calling for the transistor count to double every two years. And now, as we reach limitations on transistor size, the industry is using more brain power than the attendees at a Wordle convention in an attempt to keep the Law from being “repealed.”
Packaging is one area where we could see more innovation in the near term. The consortium hopes to establish the Universal Chiplet Interconnect Express (UCIe), to create a new ecosystem and help form other collaborations in the packaging and stacking segments. Looking for a better mousetrap in terms of chip packaging lead companies like TSMC, Samsung, and IBM to develop Vertical Transport Field Effect Transistors (VTFET) that stack vertically on a chip.

With VTFET, the transistors are placed perpendicular to each other and the current flows vertically. IBM and Samsung say that this design will also lead to less wasted energy due to greater current flow. According to the two tech firms, chips using the VTFET transistors will be able to perform twice as fast as previous components or consume 85% less energy than chips powered by FinFET transistors.

Google and AMD are also part of the consortium with Samsung, Intel, and TSMC. While Apple is not a member, the latter does rely on TSMC to build many of its chip designs including the A-series and M-series chips.



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